32 embedded the design of coprocessor of control of the system in CPU and implementation

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) 5 measure. Because dictate the movement is broken up, so unusual source also is broken up each running water line segment. For example: Addition spills over to be able to be detected in EX only unusually. Accurate and unusual processor makes accurate and unusual processing is to point to in happen unusual when, the mere right happening that dictate unusually or the instruction at the back of its undertakes unusual processing; And the instruction before its should assure to be able to end normally. Alleged " accurate " , it is that instruction that points to those who be affected by unusual processing to produce unusual condition only, all instructions before this are in before be being handled, will be carried out to finish unusually. After unusual processing ends will still from produce unusual statement to begin to continue to carry out. Operation mode switch to much progress operating system, should distinguish at least two kinds of processes: Prerogative operating system " core " of process and average order " user " process. Detect when CPU unusual when happening, dictate executive normal order can be suspended, processor enters core mode. After unusual service subprogram is carried out, CPU restores the site from inside breakpoint, continue to implement original statement series. Unusual processing automation line can decide according to afore-mentioned analysises, the main task of unusual processing automation line has hardware 3: Update corresponding CP0 register, write CP0 register namely; Save produce unusual instruction address, or it is when unusual statement when defer chamfer, save those who cause defer trough to jump turn instruction address; Choose the entrance address of unusual service subprogram. CP0 register recorded the condition with current CPU, accordingly, to CP0 register the change that writing is pair of CPU condition, need has strict control. And to register writing is the main factor that affects crucial way. Because this article basically is discussed,keep the design of the operation to CP0 register. Nextpage every register or register are certain keeping an operation is by or whether a group of unusual event happen and decide. For these each running water paragraph what arise and be received is unusual will be coded, call unusual encode, be in paragraph with undertake delivering between Duan Zhi, till MEM paragraph. In MEM paragraph, unusual encode is used at producing pair of CP0 register write make can signal, need undertakes complex decipher makes MEM paragraph lengthen, this becomes the bottleneck that raises whole CPU rate. To reduce this bottleneck, can increase to be used technically at generation to write make can the logic of signal. The unusually direct generation that each class automation line produces is written make can, compare through simple first step, no matter unusual type produces it by which, all produce 1 write make can signal. So, in MEM paragraph can avoid complex decipher, produce pair of relevant CP0 register directly write make can signal. Case of this one party used the method that changes time with the space: Fore-and-aft executive time decreased, and transverse need to increase write make can differentiate is logistic. Increase logistic function to mean need to take up more core are accumulated one-sidedly, be in the brim of whole CPU considering CP0 module, and design of completely custom-built physics is OK area of greatly cut chip, accordingly this plan has feasibility. The design of completely custom-built physics of systematic control coprocessor is in deep inferior in the integrated circuit chip of micron class, parts of an apparatus (transistor) the contribution that postpones when itself is right is smaller and smaller already, main defer depends on linking line delay. As a result of the characteristic of CP0 function, unit PC of computation of it and MMU of memory management unit, instruction has a lot of to connect a line, on these crucial method that are in even the line probably complete chip; And because CP0 is logistic more complex, the module oneself area that according to standard unit law automatic distribution wiring creates is very large, certain be about even the line in CP0 interior a lot of crooked road, the likelihood creates very great delay time. So the decision uses completely custom-built method to design the data route of CP0, control the strike that joins a line and distribution in order to go to the lavatory. Control access and data access delimit the data of the existence in running a course normally of system of fractional word circuit flows (the data that includes common sense to go up, instruction and address) flow with control. And data flows and control shedding is opposite independence: The logic that data shedding realizes is relatively plain, but a lot of data run paralell; And the logic that control sheds is more complex, great majority is 1 or a few control signal. Accordingly, control access does not use completely custom-built design commonly; And the advantage that the completely custom-built design of data access has high-powered, low power comsumption, low cost. Assisting TLB to undertake address of false or true is changed is one of main functions of CP0. TLB belongs to prerogative resource of the system, only CP0 has authority to have a visit to its, accordingly between CP0 and TLB connect a line more, data exchanges when delay more crucial also. In the meantime, the data switch of PC module and CP0 is very important also. Accordingly, CP0 unit had better stand by TLB and PC module at the same time on domain. This design is the related to TLB logic in CP0 and register independence CP0T, put between MMU and PC module; The others of CP0 returns for CP0E, put in PC bottom, make a chip namely most the lower end. If pursue,1 is shown. Graph 1.

CP0 unit and the circuit input tool that in drawing near to join sketch map circuit designs this design unitly, use are the Composer of Cadence company. When the design, in Composer is being inputted after HDL circuit of descriptive translate into is described. Next, will ensure the circuit of a design and RTL code are uniform through formal test and verify. The stand or fall that circuit designs should depend on greatly the architect's experience and skill. What the custom-built design of circuit basically points to is, design the circuit of transistor class by hand in Composer environment. Emulate tool Hspice assistance of circuit parameter to finish by the circuit of Synopsys certainly. Express the net that takes out from inside designing good circuit the input to arrive in Hspice, emulate when calculating those who give circuit, delay, revise the parameter that circuit MOS is in charge of according to Shi Yanlai again. To reduce the workload of completely custom-built design, circuit design should build the small architecture of module. Among them the main unit of CP0 is as follows certainly: Basic CP0 register (register of synchronism of the edge on clock) ; 32 comparator; 32 adder; Choose choose more implement (include 2 anthology 1, 3 anthology 1 and 4 choose 1 MUX) ; Driver (namely inverter; Its dimension parameter is changed in order to get used to) of different drive requirement. Adder introduced the idea of lead carry adder basically, divide into two module of 16 adder on whole next, carry is used to choose the thought of adder between module, raised the rate of whole circuit greatly thereby. But when its area ratio uses lead carry adder entirely, want big 20% the left and right sides. The circuit logic that the design comes out is correct, whether contented requirement is extended when, need to do functional test and verify and circuit to emulate respectively. In test and verify after the validity of each small module, need the logistic join validity between small module of test and verify, undertake test and verify to whole module finally, further analysis circuit finds out the longest way in module, through emulating, change the circuit, course that emulates again, will decide whether this module can achieve expectant logic to design a requirement. The limitation that the design of domain of completely custom-built design of domain is the requirement according to circuit function and function and craft condition (the) such as the basic figure that like the line place of equipment of wide, span, plate making allows, the domain of indispensible film of photoetching attack by surprise in designing integrated circuit to make a process. Domain design and technology of integrated circuit workmanship are linked together cheek by jowl, it is the ultimate goal that integrated circuit designs. In designing a process, what design to reduce is complex degree, use mixture design pattern, namely completely custom-built the design method that devises photograph union with standard unit. Be helpful for assuring the requirement of electric function already so, can reduce design cycle again, it is a kind of relatively ideal design mode. In completely custom-built domain, design process cent is finished for two paces, every big unit circuit always is combined by all sorts of basic circuit and become, so the first pace is scale the domain of basic circuit, DRC and LVS are done after the picture is over, assure the validity of basic circuit. The 2nd step combines big unit with these basic circuit. It is OK that completely custom-built chip designs Nextpage according to the regulation of data access circuit manual design gives reasonable territory. What each shares assure as far as possible in domain design is neat with semmetry, make its expand easily. The unit that makes connection more in the layout of domain is stood by as far as possible, shorten thereby interrelate the length of the line, when the area that reduces every unit is mixed, delay, reduce the laden electric capacity of parts of an apparatus, adopted concrete step is as follows: 1) increases the contact of the ground and underlay, power source and trap, be in aperture of many dozens of contact without parts of an apparatus and the blank that take a line, and join its and power source or ground, be helpful for collecting noise electric current, stable potential, reduce disturb and be disturbed; 2) forms network of meshy power source ground wire; The parallel that metallic thread grows in 3) avoids to be the same as a layer or getting on below two takes a line, sensitive to noise line as far as possible cloth is gotten short; 4) avoids what from beginning to end circulates to take a line; 5) is satisfying the premise that designs regulation to fall, reduce the active area area that MOS provides as far as possible, in order to reduce parasitism electric capacity, raise working rate; 6) is in data access design, should leave even the line for the metal a few reserve the position. The compositive design that controls access and data access and part of control of administrative levels of logic of test and verify use the RTL code of behavior level directly, data access part by the structured RTL code that derives from complete custom circuit, get the logic of complete module is described. Can use vector to undertake test and verify, with introduce RTL(or C model) the result that has test and verify (Trace file) undertake comparing is opposite. What administrative levels of circuit of circuit administrative levels controls access and data access is compositive and OK Composer of have the aid of is finished smoothly. To delay time information get, data access or the route that control access interior use Hspice to emulate respectively reach will integratedly obtain, whether is analytic interior put in crucial method. Involve the crucial way between data access and control access, the input that can refer interface of data access part by completely custom-built part / information is delayed when output, namely the time that this method needs in its interior. Serve as exterior tie with these information, undertake to relevant module again integrated (by module integrated) , result file lieutenant general gets compositive the crucial method after. Domain layer secondary assures the consistency of domain and circuit, need does LVS test and verify. The list of door class net that is about to dominate route guides Composer, synthesize total circuit with the complete custom circuit of data access, the Spice net list that draws circuit rank from this undertakes LVS test and verify. The tool that LVS uses is the Calibre tool of Mentor Graphics. The article basically studied epilogue to be based on the system of MIPS 4Kc architecture to control the design of coprocessor and implementation, include the implementation means of accurate and unusual processing and completely custom-built physics design. The purpose that makes when differentiate logic obtained cut and crucial ways and means, can be delayed is written through increasing in the process that controls to accurate and unusual processor, reduced the complexity that controls logic, increased the dependability of complete chip at the same time. The design of the article passed test and verify of logistic, circuit, apply in the design of 32 CPU, the 1P6M 0 of international of the core in be being used.

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