Laser applies in the small sculpture in plate making of industrial form of intaglio printing

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One, the foreword 　 flying development as photoelectron technology, range of application of laser sculpture technology is wider and wider, sculpture precision demand is higher and higher. The development level that reflects laser material treatment has the factor of 3 respects: The first it is laser technology, apply at the technique of laser parts of an apparatus that laser material processes namely; System of the 2nd machinery that is laser equipment treatment, control, namely equipment of laser beam machining; The 3rd it is level of craft of laser beam machining. Because laser technology has been very mature technology, so whether the bottleneck that the treatment craft level that has effective control and laser to laser equipment becomes laser to carve technical application. Current, the manufacturer that home produces laser technically to carve equipment is very much, their competition already changed pair of laser to equipment and the effective control that machine craft by laser technology, whether solve following problems effectively: The synchronous scanning that laser of linkage of three-dimensional graph much axis, high speed scans and advances size of width of cloth of the vibration that cause, scanning and scanning precision, laser quickly and amlposition of scanning of move back and forth, complex algorithm and problem of regular graph interpolation, had become competitive key. 2, the design that is based on DSP and FPGA is aimed at afore-mentioned all sorts of problems, combine experience of old motion pilot, we designed the motion that is based on the DSP with resourceful FPGA and powerful function to control card -- MPC03, in laser sculpture is debugged in, successful settlement afore-mentioned all sorts of problems. 1, DSP of ⑴ of 　 of MPC03 card brief introduction receives motion to dictate from lead plane or motion dictates piece, and read extraction many graph data from lead plane real time the RAM division that keeps FPGA, deliver moving state to lead plane: Condition of the position, I/O; ⑵ FPGA chip dictates according to what receive, the exercise that completes much axis electric machinery is controlled (2 dimension graph is two axes, three-dimensional graph is 3 axes) : The position, speed, interpolation, PID adjustment; ⑶ is in athletic process, FPGA synchronism reads the graphical data that takes RAM area, the basis is different ' 0 ' or ' 1 ' condition, real time ground decides whether switch is smooth, and the exterior I/O signal that collateral processing and motion concern and general I/O signal. ⑷ MPC03 blocks function index to be as follows: Highest pulse outputs frequency FH: 15MHz 　 pulse outputs frequency limits F: 0.

002 ～ 15, 000, 000Hz 　 is the smallest resolution Mmin: 0.

Frequency of 002 　 pulse installs a pace to grow R: 8191 　 of 1 ～ locate pulse counts limits R0: 0 ～ 4, 294, 967, 295 　 fall automatically R6 of limits of fast place setting: 0 ～ 4, 294, 967, tally of 295 　 increase and decrease installs limits R10: 0 ～ 4, 294, 967, 295 　 　 2. MPC03 card design and design of circuit of hardware of ⑴ of functional implementation 　 are main in MPC03 card have DSP, FPGA two functions chip, in expanded many FLASH and SRAM will store all round DSP program and data, every two FLASH and SRAM are OK and common piece choose signal CS, compositive discretion double word 32 digit undertake reading writing according to bus line, can raise the communication rate of DSP and MEMORY, configured an EPROM to store for FPGA at the same time the program of download. The chip of join DSP local bus line and PCI interface is controller of PCI bus line (PCI bridge) , it included the double mouth of a 128KBit to share memory, will realize the data switch of DSP local bus line and PCI system bus line, configured an EEPROM to store for its additionally data, at the same time this card complied with interface of Plug and Play to design a trend, expanded USB interface. The DSP that the article mentions and FPGA are operation of feebleminded bad news, low voltage, i/O signal voltage is 3.

3V, and kernel voltage is 1.

8V, configured so can output at the same time 3.

3V and 1.

8V the voltage regulator of two kinds of voltage. Consult please MPC03 blocks logistic knot composition of a picture. FPGA natural resources is sufficient, sexual price is compared tall, can the spot repeats process designing for many times, can be aimed at the specific requirement of different small lot client, agile ground modifies a design. DSP has the capacity of operation of high speed floating-point, to S- curve the data in athletic process is mixed a few interpolation are algorithmic, undertake operation is handled, cast off the dependence to the PC, correspond the data of processing in real time with FPGA. PCI interface is used more general, bus line is resourceful, communication speed piece, range of the space that find site is big. USB interface can realize off line to work, need not configure a PC for every card, industrial spot is used convenient, cost is low, accord with a times to develop a tendency. Because this program is affirmatory and proper,⑵ settles the program of the problem, four-axle function can come true on each FPGA chip identical but the operation that each other become independent each other, can achieve much axis linkage, to ichnography form and three-dimensional graph processing, can use two axes and 3 axes linkage can. In high speed motion going there and back and fast travel advance a process in, if do not add technical divisions to manage, if echelon plan institute is shown, it is in the course of high speed motion with very old acceleration, with respect to meeting occurrence vibration, concussion, the figure can appear irregular amlposition, serious when can appear of similar and moire shape be out of shape. If reduce acceleration, increase fast time (T2 - T1) very big, because machine an area to be in high speed paragraph (FH divide evenly fast paragraph) , cause effective treatment width of cloth to reduce so. To solve this problem, s curve is used in gearshift motion, can make motion is in very short time, by low speed to high speed or transfer gentlily to low speed by high speed. Through the experiment that the spot relapses, on same equipment, can greatly the treatment quality that improves work efficiency and figure. Achieve the goal of synchronous scanning to store much scanning data is mixed, the 2MBit that we used the buy inside FPGA ably piece the image data that RAM resource will come to to store every go. In this design, our open up the RAM area of the interface of 32Bit data bus line that 9 addresses line finds site, namely 16KBit. If every scanning resembles element,be 0.

1mm, press highest scanning precision, width of cloth of theoretic scanning can be achieved 1.

6m. Scan from low an address to exalted address, what go from every is low to perch ordinal undertake. Every scanning pulse, the pace stimulates bareheaded to advance into electric machinery drive one pace, read from inside RAM area at the same time take data of a graph, occupy according to reading access ' 1 ' or ' 0 ' condition decides whether switch is smooth. Because DSP keeps data of a graph to the RAM area of FPGA every time 512 × 32Bit, be opposite so during these 16KBit data processing, DSP does not need to keep data to FPGA again. Improved the work efficiency of laser equipment greatly not only, and the synchronous sex that also assured scanning, to the integral amlposition that scanning of move back and forth appears, undertake be compensatinged reversely also offerringed feasibility on software. 3, interference of interference rejection measure is the inevitable phenomenon in industrial spot and actual application, interference rejection function of the system is the important sign of systematic dependability. Printed circuit board the high aggregate that is parts of an apparatus, line, power supply cord, the stand or fall that it designs is very big to influence of interference rejection ability. Basically adopted measure of the following interference rejection in this design: Circuit of ⑴ number, model is apart: Interiorly circuit and exterior machinery use common light Ou among input signal or high speed smooth Ou undertakes keeping apart, their power source and ground wire departure. ⑵ configures digital filter: To a few signal of FPGA chip, restoration, call the police, time 0 etc, can cause systematic restoration or stop, to increase systematic dependability, want addend word filter, can come true with software here, make with VHDL language these a few signal pass trigger of D of a few class (progression inspects a condition and decide) , undertake to various signal again logic and or logistic or. 3, the last word ceaseless development as photoelectron technology and circuit of large scale integration, laser sculpture is sure to win more wide application, promote the application of DSP and FPGA in relevant domain and development then. Be in what can foreknow to will come, DSP technology and FPGA are sure to be in a lot of domain such as sculpture of spaceflight, communication, laser win more wide application, driving the further progress of these technologies then. CNC Milling CNC Machining